Patents
Our granted patents and pending applications in live trace processing, event processing, control-flow monitoring and CEDARtools.Anchor.
Some of our research results are disclosed and protected by European and US patents. This ledger distinguishes patent families from individual national or regional grants. Legal status is stated per publication or grant. The linked records and the relevant official registers provide the authoritative current status.
Patent documents describe technical subject matter at the level of generality required for legal protection. They are not implementation reports or product-performance specifications; implementation details and measured product behavior are documented separately.
A listed application establishes public disclosure of the described subject matter. A listed grant additionally establishes that patent rights were granted in the stated jurisdiction. Neither establishes that a current product implements every described embodiment, achieves a particular performance, or that another implementation infringes.
Legal status, term and claim scope are jurisdiction-specific and may depend on maintenance, procedural history and interpretation of the complete claim wording. The linked patent documents and official registers are the authoritative sources.
Trace-data processing and profiling
EP 2 873 983 B1 · US 9,286,186 B2 - granted 2016.
Cite
A. Weiss and A. Lange, "Trace-data processing and profiling device," European Patent EP 2 873 983 B1, Nov. 2, 2016.
A. Weiss and A. Lange, "Trace-data processing and profiling device," U.S. Patent 9,286,186 B2, Mar. 15, 2016.
A multi-stage pipeline for trace decoding: a message-distribution stage feeds a number of parallel message-processing stages, whose partial results are then brought back into order by a consolidation stage, using sequence identifiers and parallel buffer memories.
Reconstructing the control flow of a processor from its trace stream is not mainly a decoding problem. At GHz-class execution rates, it is a throughput problem. Each branch in the stream has to be resolved against the program image. A straightforward sequential decoder quickly reaches a throughput ceiling far below the execution rate of modern GHz-class targets.
Beyond that ceiling, the stream has to be decomposed into units that can be resolved independently, those units have to be processed in parallel, and the results have to be consolidated back into the original order. The same decomposition-and-consolidation principle can be implemented in FPGA logic or in software on a multi-core host.
EP 3 792 770 B1 · US 11,734,149 B2 - granted 2023.
Cite
A. Weiss and A. Lange, "Trace-data processing device," European Patent EP 3 792 770 B1, Nov. 8, 2023.
A. Weiss and A. Lange, "Trace-data processing device," U.S. Patent 11,734,149 B2, Aug. 22, 2023.
Branch identifiers are assigned in execution order. A branch that was not taken costs an identifier increment instead of a memory lookup; only executed branches require a lookup against the program image. This can materially reduce the random-access rate, which is a critical factor in keeping processing aligned with the incoming trace stream.
A note on decoding throughput
Accemic’s patented architecture decomposes trace processing into independently handled units and consolidates the results in execution order; the linked patents describe that approach. Product throughput is established by separate measurement records for named hardware and software configurations. If you are evaluating trace-based tooling and this is relevant to you, we are happy to talk it through.
Certain aspects of the trace-data-processing architecture are covered by granted patents. The precise scope of protection is determined by the applicable claims, read with the description and drawings, and by the law of the relevant jurisdiction. We are open to discussing licensing where appropriate.
Event processing
EP 3 792 767 B1 · US 11,321,019 B2 - granted 2023 (EP) and 2022 (US), from the same September 2019 priority as the trace-data processing device above.
Cite
A. Weiss, "Event processing," European Patent EP 3 792 767 B1, Jul. 12, 2023.
A. Weiss, "Event processing," U.S. Patent 11,321,019 B2, May 3, 2022.
Reconstruction establishes which instructions ran. It does not by itself establish what follows from that: whether a predefined condition now holds, which counter has to be incremented or which value has to be updated. This patent describes an event-processing stage for that purpose. An event-processing unit receives tokens, each carrying an event identifier and payload data; a command memory holds, per event identifier, the operations to perform - an arithmetic-logic operation, a data read or write identifier, or a flag operation - and a processing stage executes them against a data memory, an arithmetic-logic unit and a processing-control stage. Units can be chained, with the output token of one feeding the input of the next.
The purpose of that structure is the one the section above describes: keeping up with the event rate that reconstruction produces, so that results exist while the system under observation is still running, rather than after a recording has been transferred elsewhere for offline analysis.
Control-flow integrity monitoring and output containment
EP 4 016 343 B1 · US 12,462,017 B2 - granted.
Cite
A. Weiss, "Processor arrangement for monitoring control-flow integrity," European Patent EP 4 016 343 B1, Feb. 26, 2025.
A. Weiss, "Processor arrangement for monitoring control-flow integrity," U.S. Patent 12,462,017 B2, Nov. 4, 2025.
An independent monitoring engine checks the processor’s observed execution against the expected control flow. A processor-inaccessible latency buffer withholds output data while that check is performed and releases it only if no anomaly is reported; otherwise the output is blocked. The mechanism therefore turns control-flow anomaly detection into containment, preventing potentially harmful data or control commands from becoming effective before the corresponding execution has been evaluated.
Hybrid Runtime Analysis - a technical architecture for the future of embedded development (pending application)
WO/2026/162831 - published 6 August 2026, earliest priority 3 February 2025. The application is in the international phase: examination and grant occur only after entry into the national and regional phases, which has not yet taken place.
The observation approach is described on the CEDARtools.Anchor page.
Cite
A. Weiss, "Hybrid Runtime Analysis of Embedded Processors," International Patent Application WO 2026/162831 A1, published Aug. 6, 2026.
The published application describes more than the subject matter represented by the claims as published. It sets out a broader technical architecture for how we at Accemic believe embedded systems can be developed in the future.
In this architecture, machine-readable requirements, design constraints and a description of the target hardware form the starting point. Candidate source code and independent integration and system tests can be generated, compiled and executed on representative target hardware. Coverage, timing and data- and control-coupling evidence derived from real execution is mapped back to requirements and returned as machine-readable feedback for the next development iteration.
Development thereby becomes a closed, evidence-driven loop. Code and tests are generated or modified, executed on the target and evaluated against defined functional and non-functional acceptance criteria. Structural coverage is no longer only a report produced near the end of a project. It becomes a quantitative convergence signal that helps determine what must be refined next and whether the resulting system is ready for acceptance.
The application also describes requirements-based test generation kept independent of the internal implementation, sanitized coverage-gap feedback, reproducible and auditable AI-assisted synthesis, integration with continuous-integration and remote-analysis environments, and the adaptation of software and target hardware to one another.
In our view, this points to a fundamental change in embedded-systems development: away from largely separate phases of implementation, debugging and verification, and towards a continuous process in which execution evidence from real hardware guides each subsequent iteration.
The description contains further technical embodiments beyond the subject matter of the claims as published. The scope of any eventual patent protection will depend on the claims ultimately granted.
This publication is the first public step in a broader technology line that Accemic is preparing to disclose. Additional technical disclosures will be added as soon as they become public and independently citable. Each disclosed invention, its implementation and its measured effects will be documented separately.
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