Publications

Selected publications and recorded conversations we were substantially involved in.

Title	Details
Object-to-Source Mapping under Optimization: What a Control-Flow Trace Can Show, and Where Source-Level Coverage Breaks	arXiv preprint · August 2026 · open access: arXiv:2609.29656 · DOI 10.48550/arXiv.2609.29656 Alexander Weiss and Albert Schulz (both Accemic). Where the boundary lies between a complete control-flow trace of an optimized binary and source-level structural coverage: when the compiler fuses conditions or replaces a branch with a conditional select, the trace can be complete while condition-level evidence remains unresolved. The paper compares the usual remedies and describes a pre-compilation mechanism from our published patent application that keeps selected source conditions observable in the trace, demonstrated end-to-end on real silicon for an -O3 build, including a reconstructed MC/DC verdict. More on object-to-source mapping Cite A. Weiss and A. Schulz, "Object-to-Source Mapping under Optimization: What a Control-Flow Trace Can Show, and Where Source-Level Coverage Breaks," arXiv preprint arXiv:2609.29656, Aug. 2026, doi: 10.48550/arXiv.2609.29656. @misc{weiss2026objecttosource, author = {Weiss, Alexander and Schulz, Albert}, title = {Object-to-Source Mapping under Optimization: What a Control-Flow Trace Can Show, and Where Source-Level Coverage Breaks}, year = {2026}, month = aug, eprint = {2609.29656}, archivePrefix = {arXiv}, primaryClass = {cs.SE}, doi = {10.48550/arXiv.2609.29656}, url = {https://arxiv.org/abs/2609.29656} }
CTTE: An Open Dual-Protocol RISC-V^® Trace Encoder for N-Trace and E-Trace	arXiv preprint · August 2026 · open access: arXiv:2608.18170 · DOI 10.48550/arXiv.2608.18170 Alexander Weiss and Albert Schulz (both Accemic). The paper behind CEDARtools.TraceEncoder: an open SystemVerilog trace encoder with a protocol-agnostic front end and selectable N-Trace/Nexus or E-Trace back ends, integrated with six RISC-V cores and evaluated on 64-bit systems booting Linux^®, including a two-hart SMP configuration. With hardware and encoder configuration held constant, workload choice alone moves the measured trace cost from 0.21 to 4.90 bits per retired instruction. RTL, testbenches, formal properties and build scripts are released under CERN-OHL-S-2.0. Cite A. Weiss and A. Schulz, "CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace," arXiv preprint arXiv:2608.18170, Aug. 2026, doi: 10.48550/arXiv.2608.18170. @misc{weiss2026ctte, author = {Weiss, Alexander and Schulz, Albert}, title = {{CTTE}: An Open Dual-Protocol {RISC-V} Trace Encoder for {N-Trace} and {E-Trace}}, year = {2026}, month = aug, eprint = {2608.18170}, archivePrefix = {arXiv}, doi = {10.48550/arXiv.2608.18170}, url = {https://arxiv.org/abs/2608.18170} }
Towards Model-based Run-time Cybersecurity: On Control-Flow Anomaly Detection, Attack Identification, and Hardware Monitoring	arXiv preprint · August 2026 · open access: arXiv:2608.11802 · DOI 10.48550/arXiv.2608.11802 Martin Sachenbacher (OTH Regensburg), Martin Leucker (University of Lübeck), Alexander Weiss (Accemic), Aliyu Tanko Ali (University of Lübeck). Combines software-level, model-based attack identification with independent hardware monitoring of the actual control flow - the monitoring arrangement of our granted control-flow-integrity patents. A worked authentication-service example turns an ambiguous software-level diagnosis into a high-confidence identification of code injection or control-flow hijacking. More on trace-based CFI Cite M. Sachenbacher, M. Leucker, A. Weiss, and A. T. Ali, "Towards Model-based Run-time Cybersecurity: On Control-Flow Anomaly Detection, Attack Identification, and Hardware Monitoring," arXiv preprint arXiv:2608.11802, Aug. 2026, doi: 10.48550/arXiv.2608.11802. @misc{sachenbacher2026cybersecurity, author = {Sachenbacher, Martin and Leucker, Martin and Weiss, Alexander and Ali, Aliyu Tanko}, title = {Towards Model-based Run-time Cybersecurity: On Control-Flow Anomaly Detection, Attack Identification, and Hardware Monitoring}, year = {2026}, month = aug, eprint = {2608.11802}, archivePrefix = {arXiv}, doi = {10.48550/arXiv.2608.11802}, url = {https://arxiv.org/abs/2608.11802} }
Hyper Coverage with Integration Testing	Embedded World Conference 2026 · Nuremberg · conference paper Preprint (revised version): Integration-First Structural Coverage for Embedded Software: Trace-Based Evidence, Hybrid Runtime Analysis, and Cross-Variant Consolidation · arXiv:2608.13322 · August 2026 Alexander Weiss and Albert Schulz (both Accemic), Michael Wittner (Razorcat). Combines trace-derived integration coverage with TESSY unit-test evidence in one workflow. More on the integration Cite A. Weiss, A. Schulz, and M. Wittner, "Hyper Coverage with Integration Testing - How Can I Get Half of My Test Cases for Free?," presented at the Embedded World Conference, Nuremberg, Germany, Mar. 2026. A. Weiss, A. Schulz, and M. Wittner, "Integration-First Structural Coverage for Embedded Software: Trace-Based Evidence, Hybrid Runtime Analysis, and Cross-Variant Consolidation," arXiv preprint arXiv:2608.13322, Aug. 2026, doi: 10.48550/arXiv.2608.13322 (revised version of the conference paper). @inproceedings{weiss2026hypercoverage, author = {Weiss, Alexander and Schulz, Albert and Wittner, Michael}, title = {Hyper Coverage with Integration Testing -- How Can I Get Half of My Test Cases for Free?}, booktitle = {Embedded World Conference 2026}, address = {Nuremberg, Germany}, year = {2026}, month = mar } @misc{weiss2026integrationfirst, author = {Weiss, Alexander and Schulz, Albert and Wittner, Michael}, title = {Integration-First Structural Coverage for Embedded Software: Trace-Based Evidence, Hybrid Runtime Analysis, and Cross-Variant Consolidation}, year = {2026}, month = aug, eprint = {2608.13322}, archivePrefix = {arXiv}, doi = {10.48550/arXiv.2608.13322}, url = {https://arxiv.org/abs/2608.13322}, note = {Revised version of the Embedded World Conference 2026 paper} }
Dynamische Analyse für Embedded Systeme	Software Testing podcast (Richard Seidl) · October 2025 · podcast episode, in German · also on Apple Podcasts, Spotify and YouTube, linked from the episode page Alexander Weiss (Accemic) and Martin Heininger (HEICON), in conversation with host Richard Seidl. Why testing embedded systems differs from IT testing, and how hardware trace supports coverage measurement during integration tests on real hardware, without adding instrumentation to the program under test. Cite A. Weiss and M. Heininger, "Dynamische Analyse für Embedded Systeme," Software Testing podcast, episode, host R. Seidl, Oct. 28, 2025. [Online]. Available: https://www.richard-seidl.com/de/podcast/dynamische-analyse-embedded-systeme/ @misc{weiss2025dynamischeanalyse, author = {Weiss, Alexander and Heininger, Martin}, title = {Dynamische Analyse f{\"u}r Embedded Systeme}, howpublished = {Software Testing podcast, episode, host Richard Seidl}, year = {2025}, month = oct, url = {https://www.richard-seidl.com/de/podcast/dynamische-analyse-embedded-systeme/}, note = {In German. Published Oct. 28, 2025} }
Achieving Complete Structural Test Coverage in Embedded Systems Using Trace-Based Monitoring	DX 2024 · peer-reviewed conference paper · OASIcs Vol. 125 · DOI 10.4230/OASIcs.DX.2024.19 · open access (CC-BY 4.0) Alexander Weiss and Albert Schulz (both Accemic), Martin Heininger (HEICON), Martin Sachenbacher and Martin Leucker (both University of Lübeck). The scientific foundation for trace-based structural coverage - it names the MC/DC-under-optimization gap explicitly rather than working around it. Cite A. Weiss, A. Schulz, M. Heininger, M. Sachenbacher, and M. Leucker, "Achieving Complete Structural Test Coverage in Embedded Systems Using Trace-Based Monitoring," in 35th International Conference on Principles of Diagnosis and Resilient Systems (DX 2024), OASIcs, vol. 125, 2024, pp. 19:1-19:12, doi: 10.4230/OASIcs.DX.2024.19. @inproceedings{weiss2024structuralcoverage, author = {Weiss, Alexander and Schulz, Albert and Heininger, Martin and Sachenbacher, Martin and Leucker, Martin}, title = {Achieving Complete Structural Test Coverage in Embedded Systems Using Trace-Based Monitoring}, booktitle = {35th International Conference on Principles of Diagnosis and Resilient Systems (DX 2024)}, editor = {Pill, Ingo and Natan, Avraham and Wotawa, Franz}, series = {Open Access Series in Informatics (OASIcs)}, volume = {125}, pages = {19:1--19:12}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, year = {2024}, doi = {10.4230/OASIcs.DX.2024.19} }
Multi-core WCET Analysis Using Non-Intrusive Continuous Observation	ERTS² 2024 · Toulouse · conference paper · open access on HAL Daniel Kaestner, Gernot Gebhard, Markus Pister, Simon Wegener, Christian Ferdinand (all AbsInt), Albert Schulz, Alexander Weiss (both Accemic), Martin Sachenbacher, Martin Leucker (both University of Lübeck). A hybrid multi-core timing workflow: non-intrusive observation feeding TimeWeaver analysis. More on the integration of CEDARtools^® with TimeWeaver Cite D. Kästner, G. Gebhard, M. Pister, S. Wegener, C. Ferdinand, A. Schulz, A. Weiss, M. Sachenbacher, and M. Leucker, "Multi-core WCET Analysis Using Non-Intrusive Continuous Observation," presented at the Embedded Real Time Systems Congress (ERTS 2024), Toulouse, France, Jun. 2024. [Online]. Available: https://hal.science/hal-04614448v1 @inproceedings{kaestner2024wcet, author = {K{\"a}stner, Daniel and Gebhard, Gernot and Pister, Markus and Wegener, Simon and Ferdinand, Christian and Schulz, Albert and Weiss, Alexander and Sachenbacher, Martin and Leucker, Martin}, title = {Multi-core {WCET} Analysis Using Non-Intrusive Continuous Observation}, booktitle = {Embedded Real Time Systems Congress (ERTS 2024)}, address = {Toulouse, France}, year = {2024}, month = jun, url = {https://hal.science/hal-04614448v1}, note = {Open access: HAL hal-04614448} }
Everything You Always Wanted to Know About Embedded Trace	IEEE Computer 55(2), pp. 34-43, February 2022 · magazine article · IEEE Xplore Preprint: open access on TechRxiv Thomas B. Preußer (Accemic), Smitha Gautham, Abhi D. Rajagopala, Carl R. Elks (all Virginia Commonwealth University), Alexander Weiss (Accemic). The tutorial overview of embedded trace as an observability mechanism - what the trace units record, why the streams are compressed, and what that makes possible. The same ground, maintained and extended, is covered in our knowledge section. Cite T. B. Preußer, S. Gautham, A. D. Rajagopala, C. R. Elks, and A. Weiss, "Everything You Always Wanted to Know About Embedded Trace," Computer, vol. 55, no. 2, pp. 34-43, Feb. 2022, doi: 10.1109/MC.2021.3098965. @article{preusser2022embeddedtrace, author = {Preu{\ss}er, Thomas B. and Gautham, Smitha and Rajagopala, Abhi D. and Elks, Carl R. and Weiss, Alexander}, title = {Everything You Always Wanted to Know About Embedded Trace}, journal = {Computer}, volume = {55}, number = {2}, pages = {34--43}, year = {2022}, month = feb, doi = {10.1109/MC.2021.3098965} }
Understanding and Fixing Complex Faults in Embedded Cyberphysical Systems	IEEE Computer 54(1), pp. 49-60, January 2021 · magazine article · DOI 10.1109/MC.2020.3029975 Preprint: open access on arXiv Alexander Weiss (Accemic), Smitha Gautham, Athira Varma Jayakumar, Carl Elks (all Virginia Commonwealth University), D. Richard Kuhn, Raghu N. Kacker (both NIST), Thomas Preußer (Accemic). Why understanding fault types changes how debugging and runtime verification are approached - and why complex faults in embedded cyberphysical systems call for more powerful observation tools than the ones engineers traditionally had. Cite A. Weiss, S. Gautham, A. V. Jayakumar, C. R. Elks, D. R. Kuhn, R. N. Kacker, and T. B. Preußer, "Understanding and Fixing Complex Faults in Embedded Cyberphysical Systems," Computer, vol. 54, no. 1, pp. 49-60, Jan. 2021, doi: 10.1109/MC.2020.3029975. @article{weiss2021complexfaults, author = {Weiss, Alexander and Gautham, Smitha and Jayakumar, Athira Varma and Elks, Carl R. and Kuhn, D. Richard and Kacker, Raghu N. and Preu{\ss}er, Thomas B.}, title = {Understanding and Fixing Complex Faults in Embedded Cyberphysical Systems}, journal = {Computer}, volume = {54}, number = {1}, pages = {49--60}, year = {2021}, month = jan, doi = {10.1109/MC.2020.3029975} }
Using DSP Slices as Content-Addressable Update Queues	FPL 2020 · conference paper Preprint: open access on arXiv Thomas B. Preußer, Monica Chiosa (both ETH Zürich), Alexander Weiss (Accemic), Gustavo Alonso (ETH Zürich). The hardware architecture question behind live trace processing: how to keep up with a multi-gigabit stream in an FPGA. Cite T. B. Preußer, M. Chiosa, A. Weiss, and G. Alonso, "Using DSP Slices as Content-Addressable Update Queues," in 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020, pp. 121-126, doi: 10.1109/FPL50879.2020.00030. @inproceedings{preusser2020dspslices, author = {Preu{\ss}er, Thomas B. and Chiosa, Monica and Weiss, Alexander and Alonso, Gustavo}, title = {Using {DSP} Slices as Content-Addressable Update Queues}, booktitle = {2020 30th International Conference on Field-Programmable Logic and Applications (FPL)}, publisher = {IEEE}, pages = {121--126}, year = {2020}, doi = {10.1109/FPL50879.2020.00030} }