To evaluate the hidICE technology and to prove its concept, we have implemented different demonstration systems based on FPGAs and CPU soft cores.

32 Bit SPARC V8 Multi core system - up to 100 MHz

The hidICE evaluation system provides the following functionality:

  • Multi-core LEON3 SoC
  • Multiple AHB Bus Master
  • On-Chip Debug Support
  • AHB periphery

The SoC consists of

  • 3 CPUs (LEON3 core)
  • OCDs support (AHBUART and DSU3)
  • 4 AHB bus masters (3 x CPU, 1 x AHBUART)
  • Clock controller (enables clock switching while the application is running)
  • Multiprocessor Interrupt Controller
  • AHB and APB bus, AHB/APB bus bridge
  • APB Periphery: Timer, UART, I/O port, ADC
  • hidICE Sync IP (RX and TX)
  • hidICE Hash IP and comparator (system integrity control)

The ROM content will be loaded in the external memory by Accemic MDE.

The software will provide the following features:

  • System initialization
  • Test routines can be controlled by PC via OCDs
  • Handling of timer interrupts

Please contact Accemic for

  • Complete Verilog FPGA source files of the LEON3 based SPARC V8 multicore SoC system
  • Sample projects
  • Documentation

An Accemic MDE 2008 version for the SPARC V8 (LEON3) is also available.

8 Bit PicoBlaze - 200MHz

The 8 Bit hidICE demonstration system consists of 2 Xilinx Virtex4 Boards that are connected with each other via 5 LVDS lines. As CPU we chose the Xilinx PicoBlaze implementation, since conveniently, it is available completely in Verilog. The system is clocked with 200 MHz and supports asynchronous events (reset and interrupt). The hidICE demonstration system permits to record a trace, and to set break points (in the target CPU and in the emulated CPU). With an infiltrated defective instruction, the demonstration also shows the reliable functionality of the hidICE system integrity control.

32 Bit ARM Cortex M1

One of the demonstration systems consists of two Actel M1-enabled ProASIC3 boards. Using the Actel CoreConsole IP Deployment Platform a SoC was designed, consisting of a Cortex M1 core, which is connected via an AHB lite bus to a memory interface (CoreMemCtrl) and an AHB-to-APB bus bridge (CoreAHB2APB). On the APB bus a GPIO unit (CoreGPIO), an UART (CoreUARTapb) and a Timer (CoreTimer) is connected. For capturing trace data with the new technology, the system was extended by two modules.

One module (hidICE IP – Hash) calculates recursive hash values of the following AHB bus information:

  • HADDR (opcode and data adresses)
  • HRDATA (opcode and data read)

The calculation of the hash values considers the different bus states, for this purpose the HPROT[0], HWRITE, HREADY and HTRANS signals have to be interpreted.

A second module (hidICE IP - Sync TX) encodes the following information for transmission to the emulator:

  • CPU clock (SYSCLK)
  • CPU reset signal (NSYSRESET)
  • Timer interrupt signal (IRQ)
  • Data read from the APB bus (PRDATA)
  • Hash values

Due to time multiplexing of these signals, only three pins of the FPGA are required for transferring.  

The emulator core consists of the same units as the SoC except for the peripheral units. The transmitted synchronization information are decoded by the hidICE IP – Sync RX module, which provides the SYSCLK, NSYSRESET, IRQ, PRDATA and the hash values.

The emulated system is clocked with the same clock SYSCLK as the SoC. After power-on, the emulator waits for the SoC’s reset signal NSYSRESET. After receiving the reset signal, the emulator executes the same instructions as the SoC. Due to the time required for transferring the synchronization information, there is a well-defined delay of 3 SYSCLK clock cycles between SoC and emulation. In case of a read operation from the APB bus, the AHB-to-APB bus bridge of the emulator reads the same data as just read by the SoC’s AHB-to-APB bus bridge. Something similar happens in case of an interrupt: At the corresponding SYSCLK cycle in the emulator, the IRQ signal will get active and the emulator also will call the interrupt service routine.

Similar to the SoC, a hash value of the HADDR and HRDATA will be calculated. When both hash values are identical, we can be sure that the behavior of both systems is identical.

Now we can collect all trace information inside the emulator. Due to the easy access to all internal bus signals, it is possible to capture a low level bus signal trace of the AHB and the APB bus. This trace enables an extremely deep insight in the bus operation, similar to a logic analyzer. In the demonstration system the internal block RAM resources of the FPGA are used for single-shot capturing the trace data.