Is this target traceable?
The processor name is only the first input. Seven feasibility layers from core capability to metric, and the information a review actually needs.
A usable configuration requires an implemented trace source, a way to enable it, a route with sufficient bandwidth, a matching program image, attribution of observed execution to the right OS process or task where the analysis needs it, and support for the required metric.
Feasibility layers
- Core capability: which trace architecture and options can the implemented core support?
- SoC integration and security: which source, funnel, buffer, formatter and security controls are present, and can they be enabled?
- Package, board and sink: which trace pins, serial links or on-chip sinks are exposed and routed?
- Transport and bandwidth: can the complete path sustain the workload and protocol configuration?
- Executable and mapping: are the executable and compiler mapping available and compatible?
- OS, process and task context: can observed execution be attributed to the process or task that ran it? On Linux®, process and task identity may require context-ID configuration, kernel integration or an Accemic patch depending on architecture, kernel version and required analysis - verified per configuration.
- Requested metric and product support: is the requested object, source, condition, timing or CFI evidence observable in this configuration, and supported by the product?
Information to send Accemic
Exact device and package; board and revision; schematic pages or connector details; core and security state; compiler and version; executable/debug format; operating system or RTOS and kernel version where process or task attribution is required; expected clock and workload; required metric; and any restrictions on target configuration or external hardware.
The feasibility review returns the trace-source assumption, physical path, bandwidth estimate, required hardware and remaining verification steps. Start the review.
Related terminology
In this context, the following expressions refer to closely related aspects of the same question: target trace feasibility; trace feasibility check; target traceability (in the observation sense, not requirements traceability); trace-port feasibility; “can my target be traced”. This page uses target trace feasibility as the canonical term.
Related: supported targets · the trace port