CEDARtools.TraceEncoder — Open-Source Trace Encoder IP for RISC-V ®

A non-intrusive, open source tracing solution for virtually any RISC-V CPU. Based on N-Trace specification. Implemented in SystemVerilog — open source and commercial license model available.

Comprehensive Feature Set

  • Non-intrusive embedded trace
  • Highly compressed branch traces
  • Data trace for read and writes
  • Cycle accurate tracing and timestamps for inter-core synchronization
  • Various filter capabilities

Standard Interfaces

Adaptable Architecture

  • From simple single-core to multi-retire / multi-hart SoCs
  • Configurable feature set
  • Flexible system bus adapters (Wishbone, APB, AXI4, etc.)

Comprehensive Testbench

  • Rich RTL integration test suite
  • High-coverage module tests
  • Transparent example integration in existing CPU

Extra Features

  • Lightweight instrumentation using CSR trace (ACT-CAP)
  • Configurable watchpoints for custom trace events (ACT-ST)
  • Optimized trace for online processing
  • Uncompressed event output for advanced on-chip verification (e.g. control-flow integration checking)

Full Transparency

  • Publicly available on GitHub
  • Free and open-source copyleft license
  • Commercial licensing available

Why Choose CEDARtools.TraceEncoder?

Most RISC-V trace IP is a black box. The CEDARtools.TraceEncoder isn’t. It’s an open, standards-based N-Trace encoder you can read, adapt, and prove in your own SoC — with standard AMBA interfaces, an open testbench, and a real integration example rather than a datasheet promise. Built in the EU TRISTAN project and paired with an open decoder and trace format, it’s transparent end to end. Start open-source; license commercially when you need to.

Related Projects

CEDARtools.TraceEncoder

The open source trace encoder, implemented in SystemVerilog

Reference Software Decoder – NexRv

Software Nexus decoder with support for CEDARtools.TraceEncoder specific messages – Fork from riscv-nexus-trace/refcode

CTXP Format Specification

Universal trace format for architecture-agnostic trace analysis. Text and binary encoded. Including all common low level trace event types.

Contact Us

Get more information about C-Trace and commercial licensing options.

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Acknowledgment

This work was developed as part of the TRISTAN project, a European Union research initiative involving 46 partners to advance the RISC-V ecosystem. The TRISTAN project, nr. 101095947 is supported by Chips Joint Undertaking (CHIPS-JU) and its members Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey. See https://tristan-project.eu/ for more information.

RISC-V® is a registered trademark of RISC-V International. Arm and AMBA are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. Nexus 5001™ and IEEE-ISTO 5001™ are trademarks of the IEEE Industry Standards and Technology Organization (IEEE-ISTO). All other product names, logos, and brands are the property of their respective owners and are used for identification purposes only; such use does not imply affiliation with, sponsorship by, or endorsement from their respective owners. Accemic Technologies GmbH is not affiliated with, endorsed by, or certified by RISC-V International.

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