Open Source RISC-V® Trace Encoder and its Ecosystem
The open-source RISC-V® trace encoder and its ecosystem: reference decoder, CTXP format, FPGA demonstrator, Trace-Link IP, TRISTAN project.
Note: C-Trace has recently been renamed to CEDARtools.TraceEncoder (CTTE). This page stays available for existing references; the current product pages live at CEDARtools.TraceEncoder.

CEDARtools.TraceEncoder
Open source Nexus trace encoder, implemented in SystemVerilog.
Reference Decoder - NexRv
Software Nexus decoder with support for CEDARtools.TraceEncoder specific messages - fork from riscv-nexus-trace/refcode.
CTXP Format Specification
Universal trace format for architecture-agnostic trace analysis. Text and binary encoded. Including all common low level trace event types.
FPGA Demonstrator
Integrates a RISC-V® CPU with the trace encoder to demonstrate various use cases.
Trace-Link IP
Trace-Link for TSN / Ethernet; packages the trace payload into UDPv4.
TRISTAN Project
Large EU project to expand, mature and industrialize the European RISC-V® ecosystem.
This work was developed as part of the TRISTAN project, a European Union research initiative involving 46 partners to advance the RISC-V® ecosystem. The TRISTAN project, nr. 101095947 is supported by Chips Joint Undertaking (CHIPS-JU) and its members Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey. See tristan-project.eu for more information.
RISC-V® is a registered trademark of RISC-V International. Accemic Technologies GmbH is not affiliated with, endorsed by, or certified by RISC-V International.