C-Trace: Open Source RISC-V Trace Encoder and its Ecosystem

C-Trace Encoder

Open source Nexus trace encoder, implemented in SystemVerilog

Reference Decoder – NexRv

Software Nexus decoder with support for C-Trace specific messages – Fork from riscv-nexus-trace/refcode

CTXP Format Specification

Universal trace format for architecture-agnostic trace analysis. Text and binary encoded. Including all common low level trace event types.

Github

FPGA Demonstrator

Integrates RISC-V CPU with C-Trace to demonstrate various use-cases

Github

Trace-Link IP

Trace-Link for TSN / Ethernet; Package C-Trace payload to UDPv4

Github

TRISTAN Project

Large EU-project expand, mature and industrialise the European RISC-V ecosystem

tristan-project.eu

This work was developed as part of the TRISTAN project, a European Union research initiative involving 46 partners to advance the RISC-V ecosystem. The TRISTAN project, nr. 101095947 is supported by Chips Joint Undertaking (CHIPS-JU) and its members Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey. See https://tristan-project.eu/ for more information.

RISC-V® is a registered trademark of RISC-V International. Accemic Technologies GmbH is not affiliated with, endorsed by, or certified by RISC-V International.