ERTS 2024: Multi-core WCET Analysis Using Non-Intrusive Continuous Observation

We are proud to have Daniel Kästner (CTO of AbsInt) present our joint paper “Multi-core WCET Analysis Using Non-Intrusive Continuous Observation” at this year’s ERTS Congress in Toulouse.

In this paper we explain how the product bundle CEDARtools & TimeWeaver helps our customers to fulfill the objectives “MCP_Resource_Usage_3“, “MCP_Resource_usage_4“, “MCP_Software_1“, and “MCP_Software_2” objectives of EASA AMC-20-193.

Feel free to contact us and we will be happy to provide you with a copy of the paper as well as the presentation slides.

Traditional approach: All trace snippets are stored and processed. Observation time depends on trace buffer size.

New approach: Only pre-qualified trace snippets are stored and processed. No limitation in observation time.
Comparison of presented new approach vs. traditional trace captures.

Presentation at Software Quality Days 2022

Finally meeting people again sounds pretty exciting to us. The Software Quality Days 2022 in the Austria Center Vienna with the main topic “What´s The Next Big Thing in Software Engineering and Quality?” will take place 17.-19. May 2022.

We are happy to meet existing and future clients at our stand together with our partner Martin Heininger from Heicon, with whom we will present on the topic of structural coverage on higher test levels. If you are interested in the presentation topic, we from Accemic, are happy to welcome you at our stand to talk about your questions.

To book your ticket, we offer you a convenient link to the Software Quality Days 2022. If you want a discount get in touch with us to get a promo code.

We look forward to see you in Vienna.

Everything you always wanted to know about Embedded Trace

After having many of our colleagues explain again and again what “embedded trace” actually is and how essential this great feature is for the development, testing and debugging of embedded systems, we have summarised an overview for you in an article that was published on Feb 15 2022 in IEEE. We thank our co-authors from the Virginia Commonwealth University for the great cooperation for this article.

You missed our presentation at DEVCON?

A few weeks ago the mipi DEVCON was held virtually giving you the opportunity to see our presentation if you did not have the time to make it at DEVCON. Alexander Weiss and Thomas Preussler shared their knowledge of continuous online analysis of embedded trace data for safety critical systems as well as the benefits to online processing in contrast to the challenges of compressed MIPI trace protocols.

Participation as Speaker at DEVCON

This year the mipi DEVCON will be held from Sept 28-29 2021 virtually. Alexander Weiss and Thomas Preussler will have the opportunity to present their competent insights into the option of continuous online analysis of embedded trace data for safety critical systems. This also includes highlighting the benefits to online processing in contrast to the challenges of compressed MIPI trace protocols. Their presentation time slot starts at 7.35 am on Sept 29.

Join us at mipi DEVCON or get directly in touch with us for more information.

Accemic Technologies presents at mipi DEVCON

The biggest hurdle in finding problems in complex processors and thus fixing them, is the huge amount of data that needs to be analyzed without intruding into system and thus compromising the system as such. In their presentation on Sept 29 2021 at 7.35 am during mipi DEVCON, which will take place from Sept 28-29, Alexander Weiss and Thomas Preußler of Accemic Technologies will present the advantages of online analysis of the relevant trace data and show how this constitutes the basis for analyzing multicore processors in future. If this is interesting to you, but you cannot make it to the presentation, get in touch with us to get more information.

Accemic Technologies Finalist in Business Plan Competition Munich 2021

This year, Accemic Technologies invested some time and effort to produce a consistent and appealing concept in form of a business plan to get feedback on where the idea to hit the market is standing at. This plan was entered at the BayStartUP competition Munich with a price from 5.000 EUR-15.000 EUR for the 3 winners.

From 83 applicants who had to put together their ideas and present these in front of a jury in several stages, Accemic Technologies had a convincing concept that brought it to be among the 8 finalists who were gathered on a live event on 22.072021 to expect the final evaluations. Accemic Technologies is happy about the results and said they learned that the concept which is very complex to understand for non-software specialists will need an improved visualization for listeners to stand against cancer treatment and financial platforms, which are easier to understand for judges. Accemic big picture is to have their patented hardware-software implemented in every complex device world-wide.

Accemic among Speakers of Software Quality Days 2022

In the upcoming year the already known Software Quality Days will take place again. This convention is one of the most important ones in Europe if it comes to Software Quality in the Software-Cycle as a whole.

In 2022 the convention will take place under hygiene regulations according to the then then standards in the Austria Center Vienna. Accemic Technologies is proud to hold a speech in the field of Embedded Testing on the first conference day (21.1.2022). The title of the speech is “structural test on higher levels” and will start at 2.35pm. We are more than happy that Accemic Technologies will among the speakers of the Software Quality Days and will be able to show its knowledge on this day.

FPL2020 conference: Using DSP Slices as Content-Addressable Update Queues

Non-intrusive online monitoring of embedded processors can only be realized with high-end FPGA solutions.
To get an impression of the underlying complexity, check out Tom’s presentation held at the 30th International Conference on Field-Programmable Logic and Applications (FPL 2020).

Abstract: Content-Addressable Memory (CAM) is a powerful abstraction for building memory caches, routing tables and hazard detection logic. Without a native CAM structure available on FPGA devices, their functionality must be emulated using the structural primitives at hand. Such an emulation causes significant overhead in the consumption of the underlying resources, typically general-purpose fabric and on-chip block RAM (BRAM). This often motivates mitigating trade-offs, such as the reduction of the associativity of memory caches. This paper describes a technique to implement the hazard resolution in a memory update queue that hides the off-chip memory readout latency of read-modify-write cycles while guaranteeing the delivery of the full memory bandwidth. The innovative use of DSP slices allows them to assume and combine the functions of (a) the tag and data storage, (b) the tag matching, and (c) the data update in this key-value storage scenario. The proposed approach provides designers with extra flexibility by adding this resource type as another option to implement CAM.


A new technology that can be used to measure the time behavior of programs on multi-core architectures, to measure test coverage in the target system and to analyze complex errors. CEDARTOOLS is a tool offering live, non-intrusive and continuous observation of embedded processors.

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