FPL2020 conference: Using DSP Slices as Content-Addressable Update Queues

Non-intrusive online monitoring of embedded processors can only be realized with high-end FPGA solutions.
To get an impression of the underlying complexity, check out Tom’s presentation held at the 30th International Conference on Field-Programmable Logic and Applications (FPL 2020).

Abstract: Content-Addressable Memory (CAM) is a powerful abstraction for building memory caches, routing tables and hazard detection logic. Without a native CAM structure available on FPGA devices, their functionality must be emulated using the structural primitives at hand. Such an emulation causes significant overhead in the consumption of the underlying resources, typically general-purpose fabric and on-chip block RAM (BRAM). This often motivates mitigating trade-offs, such as the reduction of the associativity of memory caches. This paper describes a technique to implement the hazard resolution in a memory update queue that hides the off-chip memory readout latency of read-modify-write cycles while guaranteeing the delivery of the full memory bandwidth. The innovative use of DSP slices allows them to assume and combine the functions of (a) the tag and data storage, (b) the tag matching, and (c) the data update in this key-value storage scenario. The proposed approach provides designers with extra flexibility by adding this resource type as another option to implement CAM.

CEDARTools

A new technology that can be used to measure the time behavior of programs on multi-core architectures, to measure test coverage in the target system and to analyze complex errors. CEDARTOOLS is a tool offering live, non-intrusive and continuous observation of embedded processors.

EUROCAE

Accemic Technologies GmbH is now a full member of EUROCAE, the European leader in the development of worldwide recognised industry standards for aviation.

Presenting Effective High-Level Structural Test Solutions at ESE Kongress

Accemic will be presenting the future of efficient and effective high-level testing at this year’s ESE Kongress in Sindelfingen. Join us for our presentation and demo

“Was nach den Modul-Tests kommt
Dynamische und strukturelle Tests auf höheren Ebenen”

during the Test & Quality Session on 5-Dec-2019.

Presenting at GI Conference Echtzeit 2019

Jointly with their partners, HEICON Global Engineering and the ISP at the Universität zu Lübeck,  Accemic will be presenting their realtime system monitoring capabilities based on the on-the-fly analysis of processor execution trace data. We are delivering insights into a powerful validation and analysis solution for more efficient test workflows and effective long-term in-field monitoring. Join us for our presentation and live demo

“Test und Fehlersuche in komplexen autonomen Systemen”

at Echtzeit 2019 on 21-Nov-2019.

CEDARtools Demo at FPL 2019 in Barcelona

We are demonstrating the CEDARtools hardware platform, which is at the heart of the continuous online monitoring solution developed in the COEMS project, at the demo night of this year’s FPL conference. Come join us at our booth presenting

“The CEDARtools Platform — Massive External Memory with High Bandwidth and Low Latency under Fine-Granular Random Access Patterns”

on 11 Sep 2019 in Barcelona!

Presenting Our Requirements-Based Testing Solution at the AerospaceTechWeek

Having one of the most capable, non-intrusive system monitoring solution at hand, we show how we leverage it to build a comprehensive methodology for requirements-based testing and structural coverage. Join HEICON Gobal Engineering and Accemic Technologies in the track for Developing Next Generation Testing Strategies at the AerospaceTechWeek in Munich on Tuesday, 12 Mar 2019.

COEMS Workshop at HIPEAC 2019

Accemic will give insights to the workings of the hardware backing the non-intrusive online system monitoring solution of the COEMS consortium at the COEMS Project Workshop at the HIPEAC 2019 conference. Be invited and welcome to attend the event in Valencia starting at 2pm on Jan 21, 2019.

Public Forum: ARAMiS II Multicore Konferenz

The BMBF-funded ARAMiS II consortium is presenting their mission and their work to the public at the ARAMiS II Multicore Konferenz on 21 June 2018. The event is hosted by our project partner Vector Informatik in Stuttgart. Please, register and meet us at this public event.

Accemic Opening a New Office in Dresden, Saxony

Accemic  is expanding. We have opened a new office in Dresden, the capital of Silicon Saxony, with access to a great local talent pool and a pulsating R&D environment. Between the University of Excellence TU Dresden, several Fraunhofer Institutes and IT giants such as Globalfoundries and Infineon, we have joined the vast and lively scene of SMEs and innovative startups and have found our matching setting at the headquarter campus of TechnologieZentrumDresden near Dresden-Gostritz.

We are planning to grow our Dresden office quickly. So, watch out for our attractive job postings. We welcome applications for student internships and happily help in developing fulfilling and interesting goals for industrial master theses.