Accemic Technologies is the pioneer in Embedded Systems Dynamic Analysis.

Automated. Non-intrusive. Continuous.

Embedded systems have become an essential contribution to our modern lives. Taking over more and more demanding and critical responsibilities, these systems grow increasingly complex executing sophisticated software on powerful processors. This complexity is accompanied by an ever-increasing effort for software test. The cost of testing and debugging is approximated to be 50% of the total engineering costs. Every second hour of engineering is designated to testing. The estimated annual amount of worldwide engineering cost is up to $ 75 billion. Insufficient testing results in costly unplanned project delays and recall actions.

It is our mission at Accemic Technologies to reduce these costs of yours with the help of our innovative technology. We provide you with the means to improve the quality and reliability of your systems and to accelerate their market launch.

With the ever-increasing complexity of embedded systems, the number of software defects is also growing. Disproportionately. Even if your engineers are geniuses.

Our patented CEDARtools® live observation system helps you to control this effect.

Accemic Technologies has developed and matured CEDARtools®  a novel dynamic analysis technology. We make software tests for embedded systems more effective and efficient. We simplify the debugging process and provide you with the leverage you need to pin down the root causes of sporadic, non-deterministic failures.

CEDARtools® leverages the trace capabilities embedded into virtually all modern processors. Their trace units expose the details of the operation of the CPU and its peripherals to the outside. However, they easily produce a few GBit of trace data per second. This quickly renders approaches combining storage and offline analysis as infeasible options. We at Accemic Technologies have developed a solution that analyzes this trace-data stream in real time over an arbitrary time frame.

We provide development and test engineers with the powerful tool that boosts their productivity by enabling them to monitor a system over large time frames and to pin down even sporadic errors quickly.

Faultless systems are an unachievable challenge. Nonetheless, closing in on this ideal should be the ultimate goal of any serious project management. In addition to a well-thought-out system architecture and a thorough implementation,

  • tests as complete as possible and
  • precautions for dealing with errors in the field are important prerequisites for the ability to develop and market products on time and in the best possible quality.

Tracing Embedded Multi-Core Systems

While multi-core processors offer more processing power than single-core architectures, they are more likely to produce hard-to-detect and concurrency-related
errors. This article presents a new technology that enables the measurement of the timing behavior of programs on multi-core architectures, the measurement of
the coverage achieved by test running on the target system, and the analysis of complex errors.

Original German version of this article @ Hanser Automotive 03/2020

Structural High-Level Tests @ SAEC Days 2020

How can the completeness of integration and system tests of embedded systems be measured? This is done mathematically exact with structural tests. Unfortunately, the software instrumentation often used for this has the disadvantage of interfering with the timing of the release code and a number of other things. This is not necessarily important for module tests, but it is usually the case for higher level tests. So what to do?

In the presentation, a new observation method will be presented that non-intrusively and continuously measures the structural test coverage by means of a live synchronized digital twin. And thus provides an exact statement of how many white spots remained when the higher tests were performed. Is this non-executed code only accessible for module tests or not at all? Or is it missing one or the other test?

In addition, the deep view into the processor (without affecting the application) also allows parallel monitoring of a large number of complex timing constraints. These can be conveniently described in a high-level language and sound an alarm if, after ten hours of operation, a function has taken one microsecond too long. Without software instrumentation.

To improve the testability of an embedded system in this way, some software and hardware requirements must be taken into account when planning the system architecture. At the end of the presentation these are also explained.